The present invention generally relates to integrated circuits and more particularly to circuitry for protecting integrated circuit devices from overvoltages produced by electrostatic discharge ("ESD") events applied to the inputs of the device.
Integrated circuit ("IC") technology has advanced from generation to generation with ever decreasing circuit element dimensions and ever increasing circuit densities in the thumb-nail size semiconductor chips in which such circuits are fabricated. The thickness of insulation layers, such as gate oxide layers, has undergone a commensurate size reduction, with state-of-the-art process technologies using gate oxides under 100 .ANG. in thickness. The dielectric breakdown of such ultrathin oxide insulating layers has made these recent generation devices more sensitive to overvoltages, requiring more sophisticated overvoltage protection schemes.
A common source of overvoltages to which IC devices are exposed is ESD, which can occur merely from human contact. Such ESD events can destroy an IC device by shorting through one or more of the thin oxide insulating layers in the device. Such ESD events can produce voltage spikes in the kilovolt range. According to standard industry practice, IC devices are expected to survive an ESD event of 2 kV without damage.
A complicating factor in designing overvoltage protection circuitry is that normal system voltages, which can be communicated as inputs to the IC device, are often higher than the voltage supply levels specified for normal operation of the IC device. For example, the most recent generations of IC devices, which are made using complementary metal-oxide-semiconductor (CMOS) technology, are designed to operate using a 3.3 volt supply, whereas IC devices of earlier generations were designed to operate using a 5.0 volt supply. Many existing systems are designed around the 5.0 volt standard, such that new pieces of electronic equipment using the latest IC devices that operate on a 3.3 volt supply must be adapted to receive 5.0 volt signals. This complicates the design of ESD protection circuitry since such circuitry for devices operating with 5.0 volt supplies was designed on the assumption that any input signal in excess of 5.0 volts would be an anomaly and indicative of the onset of an overvoltage event. However, for devices operating with 3.3 volt supplies and intended to tolerate 5.0 volt input signals, such input signals could be misinterpreted as possible ESD events thus triggering overvoltage protection circuitry unless such circuitry has been redesigned to accommodate normal input signals at levels of about 1.7 volts higher than the supply voltage. As of yet, no comprehensive solution to this problem has been found.
Thus, it would be desirable to provide a more effective solution to the problem experienced by 3.3 volt IC devices receiving 5.0 volt input signals. It would be desirable to provide overvoltage protection circuitry that protects the IC device from ESD events as well as making 3.3 volt IC devices compatible with 5.0 volt systems. In order to fully appreciate the improvement in the overvoltage protection circuitry of the present invention hereinafter described, the following description of the relevant prior art is provided with reference to FIGS. 1-4.
Referring to FIG. 1, a portion of an overvoltage protection circuit used in a prior art integrated circuit device is illustrated and designated generally by reference numeral 10. The overvoltage protection circuit 10 is connected between a high voltage power bus or rail 12 and a low voltage power bus or rail 14. The high voltage rail 12 is connected to a bonding pad (not shown) that receives from an external source a high voltage supply, conventionally designated V.sub.DD. The low voltage rail 14 is connected to a bonding pad (not shown) that receives from the external source a low voltage supply or ground, conventionally designated V.sub.SS.
The integrated circuit device of which the overvoltage circuit 10 is a part includes a plurality of input bonding pads P, only two of which are shown for ease of illustration. Each such input bonding pad P is connected between diodes D.sub.1 and D.sub.2 as shown, D.sub.1 connecting the bonding pad to the low voltage rail 14 and D.sub.2 connecting the bonding pad to the high voltage rail 12. An overvoltage appearing on an input bonding pad P can be either a positive or negative voltage. The diodes D.sub.1 and D.sub.2 provide one form of overvoltage protection for the IC drive, diodes D.sub.2 turning on to couple the input bonding pads to the V.sub.DD rail 12 when the overvoltage is positive and diodes D.sub.1 turning on to couple the input bonding pads to the V.sub.SS rail 14 when the overvoltage is negative. In practice, each diode D.sub.1 and diode D.sub.2 are actually sets of relatively large diodes (e.g., four per set connected in parallel), providing low impedance ESD conduction paths from the input bonding pads P to the V.sub.DD and V.sub.SS rails.
The signal on each input bonding pad P is communicated to a corresponding receiver circuit 16 (labeled "Re") through a node 18 disposed between the input bonding pad P and the anode of the corresponding diode D.sub.2 as shown. An ESD clamp 20 corresponding to each input bonding pad P is connected between the node 18 and the low voltage rail 14. Along with output circuits (not shown) the receiver circuits 16 comprise the sensitive input/output circuitry of the device that requires protection from overvoltages coming from external sources.
The ESD clamp 20 used to clamp each input bonding pad P is normally nonconductive but is triggered to become conductive in response to an ESD event appearing on the input bonding pads. Short duration voltage transients of several thousand volts can arise from human or machine handling of the IC device prior to installation in its end-use equipment. High voltage transients can arise from other sources after the IC device is installed in its end-use equipment. When an input bonding pad P experiences an ESD event, its ESD clamp 20 is triggered and quickly becomes conductive to limit the voltage differential seen by circuit elements of the IC device to a relatively low level that does not damage sensitive structures of the device. This ESD protection scheme requires an ESD clamp 20 for each input bonding pad P, and therefore requires a commitment of considerable chip space to implement.
One implementation of a suitable ESD clamp known in the art is shown in FIG. 2. The ESD clamp 20 of FIG. 2 has an N-channel MOS transistor T.sub.C connected between node 18 and the V.sub.SS rail 14. A circuit for triggering transistor T.sub.C includes a Zener diode Z, resistors R.sub.1 and R.sub.2 and a diode D connected in series between node 18 and the V.sub.SS rail 14. A node 22 is connected between resistors R.sub.1 and R.sub.2 to the gate of transistor T.sub.C. The Zener diode Z has its cathode connected to node 18 and its anode connected to resistor R.sub.1. Diode D has its anode connected to resistor R.sub.2 and its cathode connected to the V.sub.SS rail 14. Transistor T.sub.C has a parasitic bipolar mode of operation designated by transistor Q.sub.C shown in dashed outline. Transistor T.sub.C is made very wide with a short channel length so that it is capable of efficiently shunting the relatively high currents characteristic of an ESD event.
The values of elements Z, R.sub.1, R.sub.2 and D are chosen so that the gate of transistor T.sub.C will see a voltage of about 3 volts when an ESD event occurs and the voltage on node 18 rises above a trigger voltage of about 7.0 to 7.5 volts. Once transistor T.sub.C is turned on by such an ESD event, bipolar conduction through transistor Q.sub.C will occur and will continue until the voltage on node 18 falls below the trigger voltage level. A more complete explanation of the operation of this particular ESD clamp 20 is provided in U.S. patent application entitled "Overvoltage Protection Device for MOS Integrated Circuits," Ser. No. 08/712,058, filed Sep. 10, 1996.
Another ESD clamp or shunt intended for use as part of a CMOS integrated circuit output circuit is described in U.S. Pat. No. 5,173,755, issued Dec. 22, 1992. A protection circuit for shunting between the power rails is described in U.S. Pat. No. 5,237,395, issued Aug. 17, 1993. Additionally, U.S. Pat. No. 5,124,877, issued Jun. 23, 1992, describes an electrostatic discharge protection circuit that includes a discharge reference rail that is connected to the positive power supply terminal (V.sub.DD) by a level shifter circuit, which shunts the excess voltage of an ESD event from the input bonding pads to the positive power supply terminal. It is preferable, however, to shunt a positive ESD event to the negative power supply terminal (V.sub.SS), as occurs using the ESD clamp 20 of FIGS. 1 and 2 herein.
The transistor T.sub.C shown in FIG. 2 may be implemented by the structure shown in FIG. 3, in which the transistor is designated generally by reference numeral 30. It has become standard practice in the art to fabricate MOS transistors with source and drain regions having both lightly doped and heavily doped portions. Such transistors are known as lightly doped drain ("LDD") transistors. By a slight modification of the fabrication process, the transistor 30 of FIG. 3 can be made with characteristics that are advantageous when used in an ESD clamping circuit.
In FIG. 3, transistor 30 is shown in cross section as including doped regions formed in a monocrystalline silicon substrate (shown partially broken away) with a gate structure constructed thereon. In particular, N+ doped source and drain regions 32 and 34 are formed in a P well 36, the entire structure being formed atop an N-type major body portion 38 of the substrate. A polycrystalline silicon ("polysilicon") gate 40 is formed atop a gate oxide layer 42, which is grown on the top surface of the substrate between the source and drain regions 32 and 34. Spacer oxide layers 44 and 46 are used in the course of processing to define the edges of the source and drain regions 32 and 34, which are formed by an ion implantation step. Ordinarily, in conventional processes, a light dose of an N-type dopant (e.g., phosphorus) is implanted prior to formation of the spacer oxide layers 44 and 46. Such a conventional light dose implant produces lightly dope drain regions in the locations indicated by the dashed regions 48. Such LDD regions 48 normally extend under the gate 40 and define a channel region therebetween.
When it is desired to form modified transistor 30, the light dose ion implantation can be prevented from reaching the silicon surface at the site of transistor 30 by providing a mask covering that site, thereby producing the structure depicted in FIG. 3. Lacking the conventional LDD regions 48, transistor 30 has a higher than normal turn-on threshold voltage in the range from about 1.2 to 2.0 volts. A normal turn-on threshold voltage is about 0.6 volts. The higher turn-on threshold voltage of modified transistor 30 is due to the small gaps between the edges of the gate 40 and the facing edges of the N+ source and drain regions 32 and 34.
Referring again to FIG. 2, when transistor T.sub.C is fabricated as just described without the conventional LDD regions, it can be advantageously employed in the ESD clamp 20. A conventional N-channel transistor having LDD implants could be damaged by the relatively high parasitic conduction that occurs in an ESD event. The relatively high currents going through the leading edges of the LDD regions can damage the silicon at such points causing the transistor to fail immediately or become excessively leaky and lead to a subsequent failure. Using a modified transistor 30 without the conventional LDD regions for transistor T.sub.C provides a more rugged transistor capable of relatively high, nondestructive parasitic conduction.
Now referring to FIG. 4, the details of a common implementation of a receiver circuit, which was designed for use with a 5.0 volt V.sub.DD supply, is shown in the dashed outline labeled by reference numeral 16. The receiver circuit 16 may be one of various similar receiver circuits that may be protected by the overvoltage protection circuit 10 of FIG. 1. One input bonding pad P and its respective set of diodes D.sub.1 and D.sub.2 are shown in FIG. 4 connected to the receiver circuit 16. A signal line 50 connects the input bonding pad P to an input node 52 of the receiver circuit 16. A CMOS inverter consisting of N-channel MOS transistor T.sub.1 and P-channel MOS transistor T.sub.2 is connected between the V.sub.DD and V.sub.SS power rails. The CMOS inverter has an input node 54 connecting the gates of transistors T.sub.1 and T.sub.2 and an output node 56 connecting the drains of transistors T.sub.1 and T.sub.2. The output node 56 is the receiver output node that communicates with other circuitry (not shown) of the IC device. The source of transistor T.sub.1 and its P well are connected to the V.sub.SS rail. The source of transistor T.sub.2 and its N well are connected to the V.sub.DD rail.
Resistors R.sub.3 and R.sub.4 connect the inverter input node 54 to the receiver input node 52. Resistor R.sub.3 is formed in the substrate in a P+ region set in an N well, which is connected to the V.sub.DD rail. The PN junction between the P+ resistor region and its N well defines a diode D.sub.3 connected to the V.sub.DD rail. Resistor R.sub.4 is formed in the substrate in an N+ region set in a P well, which is connected to the V.sub.SS rail. The PN junction between the N+ resistor region and its P well defines a diode D.sub.4 connected to the V.sub.SS rail. The resistance values for resistors R.sub.3 and R.sub.4 are each about 100 to 150 ohms, providing a total resistance of about 200 to 300 ohms in the path between the receiver input node 52 and the inverter input node 54.
If an ESD event occurs at bonding pad P, the relatively large diodes D.sub.1 and D.sub.2 provide primary ESD protection together with the ESD clamp 20 of FIG. 1. The resistors R.sub.3 and R.sub.4, shown in FIG. 4, provide additional protection for transistors T.sub.1 and T.sub.2. However, it is known that transistors T.sub.1 and T.sub.2 are overvoltage-sensitive, and that they are often the site of device failure.
The inventors have found, on some devices that had essentially the same ESD protection circuitry and receiver circuitry, a correlation between ESD immunity and the length of the signal line connecting the input bonding pad and the receiver input node. This length corresponds to that shown as the dimension X in the circuit of FIG. 4. When the receiver circuit was placed very close to the input bonding pad, the integrated circuit devices had a lower ESD protection capability than when the receiver circuit was placed at a greater distance X from the input bonding pad.
Certain integrated circuit devices had their receiver circuits placed about 350 microns from their input bonding pads. These devices were found to have ESD protection ratings well over 2 kV. The devices in which the receiver circuits were placed close to their input bonding pads P exhibited ESD protection ratings that fell significantly under 2 kV.